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Semiconductor
NOT
October 1998
N FOR DED 1179 N MME ee HI S ECO R
E
ES WD
IGN
S
HI1176
8-Bit, 20 MSPS, Flash A/D Converter
Description
The HI1176 is an 8-bit, CMOS analog-to-digital converter for video use that features a sync clamp function. The adoption of a 2-step parallel method realizes low power consumption and a maximum conversion speed of 20 MSPS. For higher sampling rates, refer to the pin-for-pin compatible HI1179 data sheet, AnswerFAX document number 3666.
Features
* Resolution 0.5 LSB (DNL) . . . . . . . . . . . . . . . . . . . 8-Bit * Maximum Sampling [ /Title (HI1176) Frequency . . . . . . . . . . . 20 MSPS
/Subject (8-Bit, 20 MSPS, Flash A/D Converter) * Low Power Consumption at 20 MSPS (Typ) (Reference /Author () Current Excluded) . . . . . . . . . . . . . . .60mW /Keywords (Harris Semiconductor, * Built-In Sync Clamp Function
Video, Image Scanner, PC Video capture, Set top box,Clamp Pulse * Built-In Monostable Multivibrator for Clamp, Internal RefApplications erence) Generation * Video Digitizing /Creator () Pulse Polarity Selection Function * Built-In Sync * Image Scanners /DOCINFO pdfmark
* Clamp Pulse Direct Input Possible * /PageMode /UseOutlines [ Built-In Clamp ON/OFF Function * Built-In Reference Voltage Self Bias Circuit /DOCVIEW pdfmark * Input CMOS Compatible * Three-State TTL Compatible Output * Single +5V Power Supply * Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . 11pF * Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 300 * Direct Replacement for the Sony CXD1176
HI1176JCQ HI1176-EV
* Low Cost High Speed Data Acquisition Systems * Multimedia
Ordering Information
PART NUMBER TEMP. RANGE (oC) -40 to 85 25 PACKAGE 32 Ld MQFP PKG. NO. Q32.7x7-S
Evaluation Board
Pinout
HI1176 (MQFP) TOP VIEW
VRBS DVSS DVSS VREF CCP CLE OE NC (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
VRB AVSS AVSS VIN AVDD AVDD VRT VRTS
NC
DVDD
DVDD
SYNC
AVDD
CLK
SEL
PW
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1998
File Number
3582.5
4-1
HI1176 Functional Block Diagram
28 OE 30 DVSS 31 D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) 1 2 3 4 5 6 7 8 UPPER DATA LATCHES LOWER DATA LATCHES LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) DVSS REFERENCE SUPPLY 25 VRBS 24 VRB 23 AVSS 22 AVSS 21 VIN LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATOR (4-BIT) 20 AVDD 19 AVDD 18 VRT UPPER ENCODER (4-BIT) UPPER SAMPLING COMPARATOR (4-BIT) 17 VRTS 16 AVDD
DVDD 10 DVDD 11 CLK 12 CLOCK GENERATOR
NC
9
-
+ 15 PW 14 SYNC M*M 29 27 26 13 SEL
NC 32
CLE CCP VREF
Typical Application Schematic
WHEN CLAMP IS NOT USED (SELF BIAS USED)
+5V (DIGITAL) HCO4 CLOCK IN 0.1F
+5V (ANALOG)
0.01F
16 15 14 13 12 11 10 9 8 17 18 19 20 7 6 5 4 3 2
D7 D6 D5 D4 D3 D2 D1 D0
VIDEO IN
75 0.1F 10pF 0.01F
21 22 23
1 24 25 26 27 28 29 30 31 32
GND (ANALOG) +5V (DIGITAL)
GND (DIGITAL)
4-2
HI1176
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT , VRB . . . . . . . . . VDD + 0.5V to VSS - 0.5V Analog Input Voltage, VIN . . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Input Voltage, CLK. . . . . . . . . . . . . VDD + 0.5V to VSS - 0.5V Digital Output Voltage, VOH , VOL . . . . . . . VDD + 0.5V to VSS - 0.5V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions (Note 1)
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS , DVDD , DVSS . . . . . . . . . . . . . . . +4.75V to +5.25V |DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below Analog Input Voltage, VIN . . . . . . . . . VRB to VRT (1.8VP-P to AVDD) Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Offset Voltage EOT EOB Integral Non-Linearity, INL Differential Non-Linearity, DNL DYNAMIC CHARACTERISTICS
fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) TEST CONDITIONS MIN TYP MAX UNIT
-60 +20 fC = 20 MSPS, VIN = 0.5V to 2.5V fC = 20 MSPS, VIN = 0.5V to 2.5V -
-40 +40 0.5 0.3
-20 +60 1.3 0.5
mV mV LSB LSB
Signal to Noise Ratio, SINAD RMS Signal --------------------------------------------------------------------------------------------------------------Signal-To -Noise + Distortion Ratio, SINAD Maximum Conversion Speed, fC Minimum Conversion Speed Differential Gain Error, DG Differential Phase Error, DP Aperture Jitter, tAJ Sampling Delay, tDS ANALOG INPUTS Analog Input Bandwidth (-1dB), BW Analog Input Capacitance, CIN
fS = 20MHz, fIN = 1MHz fS = 20MHz, fIN = 3.58MHz VIN = 0.5V to 2.5V, fIN = 1kHz Ramp
20 -
46 46 35 1.0 0.5 30 4
0.5 -
dB dB MSPS MSPS % Degree ps ns
NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS
-
VIN = 1.5V + 0.07VRMS -
18 11
-
MHz pF
4-3
HI1176
Electrical Specifications
PARAMETER REFERENCE INPUT Reference Pin Current, IREF Reference Resistance (VRT to VRB), RREF INTERNAL VOLTAGE REFERENCES Self Bias VRB VRT - VRB DIGITAL INPUTS Digital Input Voltage VIH VIL Digital Input Current IIH IIL DIGITAL OUTPUTS Digital Output Current IOH IOL Digital Output Current IOZH IOZL TIMING CHARACTERISTICS Output Data Delay, tDL POWER SUPPLY CHARACTERISTIC Supply Current, IDD CLAMP CHARACTERISTICS Clamp Offset Voltage, EOC VIN = DC, PWS = 3s VREF = 0.5V VREF = 2.5V Clamp Pulse Width (Sync Pin Input), tCPW Clamp Pulse Delay, tCPD NOTE: 1. Electrical specifications guaranteed only under the stated operating conditions. C = 100pF, R = 130k on Pin 15 0 -50 1.75 +20 -30 2.75 25 +40 -10 3.75 mV mV s ns fC = 20 MSPS, NTSC Ramp Wave Input 12 18 mA 18 30 ns OE = VDD , VDD = Max VOH = VDD VOL = 0V 16 16 A A OE = VSS , VDD = Min VOH = VDD -0.5V VOL = 0.4V -1.1 3.7 mA mA VDD = Max VIH = VDD VIL = 0V 5 5 A A 4.0 1.0 V V Short VRB and VRBS , Short VRT and VRTS 0.48 1.96 0.52 2.08 0.56 2.22 V V 4.5 230 6.6 300 8.7 450 mA fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT
4-4
HI1176 Timing Diagrams
tPW1 tPW0
CLOCK ANALOG INPUT
N
N+1
N-2 N-1
N+3 N
N+4 N+1
DATA OUTPUT
N-3
N-2
: POINT FOR ANALOG SIGNAL SAMPLING
tD = 18ns
FIGURE 1.
VI (1)
VI (2)
VI (3)
VI (4)
ANALOG INPUT
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
S (1)
C (1)
S (2)
C (2)
S (3)
C (3)
S (4)
C (4)
UPPER DATA
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
RV (0)
RV (1)
RV (2)
RV (3)
LOWER COMPARATOR BLOCK A
S (1)
H (1)
C (1)
S (3)
H (3)
C (3)
LOWER DATA A
LD (-1)
LD (1)
LOWER COMPARATOR BLOCK B
H (0)
C (0)
S (2)
H (2)
C (2)
S (4)
H (4)
LOWER DATA B
LD (-2)
LD (0)
LD (2)
DIGITAL OUTPUT
OUT (-2)
OUT (-1)
OUT (0)
OUT (1)
FIGURE 2.
4-5
HI1176 Typical Performance Curves
20 VPP = 5.0V, VRT = 2.5V, VRB = 0.5V TA = 25oC, VIN = 2VP-P POWER DISSIPATION (mW) 20 15 IDD (mA) IDD (mA) 15 100
10
10 5
50
4.0
4.5
5.0
5.5
5
0
5
10
15
20
25
30
35
POWER SUPPLY VOLTAGE (V)
SAMPLING RATE (MSPS)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING RATE
1.4 DIFFERENTIAL NON-LINEARITY (LSB)
TA = 25oC, VRT = 2.5V, VRB = 0.5V VDD = 5.0V, fS = 20 MSPS
1.0
0.6
0.2 0 0 2 4 6 8 10 INPUT FREQUENCY (MHz)
FIGURE 5. DIFFERENTIAL NON-LINEARITY vs INPUT FREQUENCY
Pin Descriptions
PIN NUMBER 1-8 SYMBOL D0 to D7 EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D7 (MSB) Output.
D1
10, 11
DVDD
Digital +5V.
4-6
HI1176 Pin Descriptions
PIN NUMBER 12 (Continued)
SYMBOL CLK
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Clock Input.
12
DVSS
13
SEL
DVDD
When SEL is low, the falling edge of Pin 14 (sync) triggers the monostable. When SEL is high, the rising edge of Pin 14 (sync) triggers the monostable.
13
DVSS
14
SYNC
DVDD
Trigger pulse input to the monostable multivibrator. Trigger polarity can be controlled by Pin 13 (SEL).
14
DVSS
15
PW
DVDD
15
When a clamp pulse is generated by the monostable, the pulse width is determined by the external R and C. When the clamp pulse is directly input, it is input to Pin 15 (PW).
DVSS
16, 19, 20 17
AVDD VRTS
AVDD
Analog +5V. When shorted with VRT , generates approx. +2.6V.
17
18 24
VRT VRB
18
AVDD
Reference Voltage (Top). Reference Voltage (Bottom).
24
AVSS
4-7
HI1176 Pin Descriptions
PIN NUMBER 21 (Continued)
SYMBOL VIN
EQUIVALENT CIRCUIT
AVDD
DESCRIPTION Analog Input.
21
AVSS
22, 23 25
AVSS VRBS
AVSS
Analog Ground. When shorted with VRB , generates approx. +0.5V.
25
26
VREF
AVDD
Clamp Reference Voltage Input.
26
AVSS
27
CCP
AVDD
Integrates the voltage for clamp control.
27
AVSS
28, 31 29
DVSS CLE
DVDD
Digital GND. When CLE is low, clamp function is activated. When CLE is high, clamp function is OFF and only the usual A/D converter function is active. By connecting CLE pin to DVDD via a several hundred resistance, the clamp pulse can be tested.
29
DVSS
CLAMP PULSE
30
OE
DVDD
When OE is low, data is valid. When OE is high, D0 to D7 pins are high impedance.
30
DVSS
4-8
HI1176
TABLE 1. A/D OUTPUT CODE INPUT SIGNAL VOLTAGE VRT * * * * * * * * VRB DIGITAL OUTPUT CODE STEP 255 * * * 128 127 * * * 0 0 0 0 0 1 0 0 1 0 1 0 1 MSB 1 1 1 1 1 * * * 0 1 * * * 0 0 0 0 0 1 0 1 0 1 1 1 LSB 1
Detailed Description
The HI1176 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling/autozero (S), hold (H), and compare (C). The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT -VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Power, Grounding, and Decoupling To reduce noise effects, separate the analog and digital grounds. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1F capacitor close to the pin. Analog Input The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation, it may be necessary to insert a resistor between the output of the amplifier and the A/D input. Reference Input The range of the A/D is set by the voltage between VRT and VRB . The internal bias generator will set VRTS to 2.5V and VRBS to 0.5V. These can be used as the part reference by shorting VRT and VRTS and VRB to VRBS . The analog input range of the A/D will now be from 0.5V to 2.5V. If a VRB below +0.5V is used the linearity of the part will be degraded. Bypass VRT and VRB to analog ground with a 0.1F capacitor. Clamp Operation The HI1176 provides a clamp option that allows the user to clamp a portion of the analog input to a voltage set by the VREF pin. The clamp function is enabled by bringing CLE low. An internal monostable multivibrator is provided that can be used to generate the clamp pulses. The monostable pulse width is determined by the external R and C connected to the PW pin. The trigger to the monostable is applied on the SYNC pin. The edge that triggers the monostable is determined by the SEL pin. When SEL is low the falling edge will trigger the monostable and when SEL is high the rising edge will trigger the monostable. Figure 6 shows the HI1176 configured for this mode of operation. The clamp pulse is latched by the ADC sampling clock. This is not necessary to the operation of the clamp function but if this is not done then a slight beat might be generated as vertical sag according to the relation between the sampling frequency and the clamp frequency. The HI1176 can also be configured to operate with an external clamp pulse. In this case a negative going pulse is input to the PW pin. VIN will now be clamped during the low period of the clamp pulse to the voltage on the VREF pin. Figure 7 shows the HI1176 configured for this mode of operation. Figure 1 illustrates the operation of HI1176 when the clamp function is not used.
4-9
HI1176 Typical Application Circuits
+5V (DIGITAL)
HCO4 CLOCK IN
0.1F
CK SYNC IN LATCH Q 16 15 14 13 12 11 10 9 8 17 18 19 VIDEO IN 10F + 10pF 0.01F 75 0.1F 20 21 22 23 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 D1 D0
+5V (ANALOG)
0.01F
1 24 25 26 27 28 29 30 31 32 +5V (ANALOG)
VREF 20K 0.01F GND (ANALOG) GND (DIGITAL)
FIGURE 6. PEDESTAL CLAMP IS EXECUTED BY SYNC PULSE (SELF BIAS USED)
+5V (DIGITAL) HCO4 CLOCK IN CK CLAMP PULSE IN LATCH Q 16 15 14 13 12 11 10 9 8 17 18 19 VIDEO IN 10F + 10pF 0.01F 75 0.1F 20 21 22 23 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 D1 D0 0.1F
+5V (ANALOG)
0.01F
1 24 25 26 27 28 29 30 31 32 +5V (ANALOG)
VREF 20K 0.01F GND (ANALOG) GND (DIGITAL)
FIGURE 7. CLAMP PULSE IS DIRECTLY INPUT (SELF BIAS USED)
4-10
HI1176 Test Circuits
+V
S2
+ S1
S1 : ON IF A < B S2 : ON IF A > B
-V AB 8 COMPARATOR A8 A1 A0 B8 B1 B0 BUFFER
"0" DVM CLK (20MHz)
"1" 8 000 * * * 00 TO 111 * * * 10
CONTROLLER
FIGURE 8. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT
2.6V fC -1kHz SG 0.6V 1 2 NTSC SIGNAL SOURCE 40 IRE MODULATION BURST 0.6V -5.2V TTL fC ECL AMP VIN DUT HI1176 8 TTL ECL 620 2.6V -5.2V 620 SYNC DG DP 8 HI20201 1 10-BIT D/A CLK 2 VECTOR SCOPE HPF
ERROR RATE
COUNTER
100
IRE 0 -40 SG (CW)
FIGURE 9. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
2.6V 0.6V
VDD VRT VIN VRB CLK OE GND VOL
2.6V IOL 0.6V
VDD VRT VIN VRB CLK
IOH
+
OE GND
VOH
+
-
-
FIGURE 10. DIGITAL OUTPUT CURRENT TEST CIRCUIT
4-11

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